# HDLBits – Module fadd

In this exercise, you will create a circuit with two levels of hierarchy. Your top_module will instantiate two copies of add16 (provided), each of which will instantiate 16 copies of add1 (which you must write). Thus, you must write two modules: top_module and add1.

Like module_add, you are given a module add16 that performs a 16-bit addition. You must instantiate two of them to create a 32-bit adder. One add16 module computes the lower 16 bits of the addition result, while the second add16 module computes the upper 16 bits of the result. Your 32-bit adder does not need to handle carry-in (assume 0) or carry-out (ignored).

Connect the add16 modules together as shown in the diagram below. See the HDLBits website for a diagram.

Full adder equations:
sum = a ^ b ^ cin
cout = a&b | a&cin | b&cin

https://hdlbits.01xz.net/wiki/Module_fadd

This exercise is much easier than it looks. Once again, just make sure to implement the modules as they’re represented in the diagrams on the HDLBits website.

It turns out that the top_module module is exactly the same as in the last exercise. As a result, only the add1 module needs to be created.

As a sidenote, remember that it’s typically not a good idea to include multiple modules in a single file, which is what is being done here. In practice, you would have two separate files, which would be top_module.sv and add1.sv.

module top_module (
input  logic [31:0] a, b,
output logic [31:0] sum );
// Define internal logic
logic cout_low;
logic [15:0] sum_high, sum_low;

// Module instantiations
add16 add16_low_i (
.a    (a[15:0]),
.b    (b[15:0]),
.cin  ('0),
.sum  (sum_low),
.cout (cout_low) );
add16 add16_high_i (
.a    (a[31:16]),
.b    (b[31:16]),
.cin  (cout_low),
.sum  (sum_high),
.cout () );
// Assign output logic
assign sum = {sum_high, sum_low};

endmodule : top_module

module add1 (
input  logic a, b,
input  logic cin,
output logic sum,
output logic cout );
// Full adder module here
assign sum  = a ^ b ^ cin;
assign cout = ( a & b ) | ( a & cin ) | ( b & cin );
endmodule : add1