aYou are given a module
my_dff
with two inputs and one output (that implements a D flip-flop). Instantiate three of them, then chain them together to make a shift register of length 3. Theclk
port needs to be connected to all instances.The module provided to you is:
module my_dff ( input clk, input d, output q );
Note that to make the internal connections, you will need to declare some wires. Be careful about naming your wires and module instances: the names must be unique.
Note: See the HDLBits page for a diagram.
https://hdlbits.01xz.net/wiki/Module_shift
I’m going to make port connections by name. This solution is significantly longer than connecting ports by position, but it much more maintainable, in my opinion.
module top_module (
input logic clk,
input logic d,
output logic q );
// Define internal logic
logic q0, q1, q2;
my_dff dff0_i (
.clk(clk),
.d(d),
.q(q0) );
my_dff dff1_i (
.clk(clk),
.d(q0),
.q(q1) );
my_dff dff2_i (
.clk(clk),
.d(q1),
.q(q2) );
// Output assignment
assign q = q2;
endmodule : top_module