Create a module that implements a NOT gate.
This circuit is similar to wire, but with a slight difference. When making the connection from the wire
into the wire
outwe’re going to implement an inverter (or “NOT-gate”) instead of a plain wire.
Use an assign statement. The
assignstatement will continuously drive the inverse of
Hint: Verilog has separate bitwise-NOT (https://hdlbits.01xz.net/wiki/Notgate
~) and logical-NOT (
!) operators, like C. Since we’re working with a one-bit here, it doesn’t matter which we choose.
In this case, we have 1-bit input and output ports, so we can use either of the logical (!) or bitwise (~) NOT operators. However, as a general rule and to set you up for natural success in the future, I’ll be pulling a quote from ya’boi Pong P. Chu:
Since SystemVerilog uses 0 and 1 to represent the false and true values, bitwise and logical operators can be used interchangeably in some situations. However, it is good practice to use logical operators for Boolean expressions and use bitwise operators for signal manipulation.FPGA Prototyping by SystemVerilog Examples Xilinx Microblaze MCS SOC Edition – Pong P. Chu – pg. 33
Bearing this in mind, and since we’re performing signal manipulation, the optimal solution is as follows:
module top_module ( input logic in, output logic out ); assign out = ~in; endmodule : top_module