HDLBits – Vector0

Build a circuit that has one 3-bit input, then outputs the same vector, and also splits it into three separate 1-bit outputs. Connect output o0 to the input vector’s position 0, o1 to position 1, etc.

In a diagram, a tick mark with a number next to it indicates the width of the vector (or “bus”), rather than drawing a separate line for each bit in the vector.

https://hdlbits.01xz.net/wiki/Vector0

There isn’t much that’s new in this exercise. The main takeaway as that n-bit logic vectors can be assigned in the same ways as the 1-bit logic signals that we’ve been working with up to this point. This exercise also introduces part select, which allows you to access an element or a ranged subset of a given logic vector.

module top_module (
  input  logic [2:0] vec,
  output logic [2:0] outv,
  output logic o2,
  output logic o1,
  output logic o0 );
  // 3-bit vector assignment
  assign outv = vec;
  
  // 1-bit assignments using part select
  assign o2 = vec[2];
  assign o1 = vec[1];
  assign o0 = vec[0];
endmodule : top_module

This solution can be simplified by using concatenation to drive outputs o2, o1, and o0. Concatenating these signals will create a 3-bit vector, which will be the same size as the vec input. Remember that concatenation can be used on either side of an assign statement, but this won’t be necessary here.

module top_module (
  input  logic [2:0] vec,
  output logic [2:0] outv,
  output logic o2,
  output logic o1,
  output logic o0 );
  // 3-bit vector assignment
  assign outv = vec;
  
  // 1-bit output assignments using concatenation
  assign {o2, o1, o0} = vec;
endmodule : top_module