Given five 1-bit signals (a, b, c, d, and e), compute all 25 pairwise one-bit comparisons in the 25-bit output vector. The output should be 1 if the two bits being compared are equal.

out[24] = ~ a ^ a; // a == a, so out[24] is always 1.

out[23] = ~ a ^ b;

out[22] = ~ a ^ c;

…

out[ 1] = ~ e ^ d;

out[ 0] = ~ e ^ e;Hint: See the HDLBits website for a diagram of what needs to be done.

https://hdlbits.01xz.net/wiki/Vector5

The purpose of this exercise is to reinforce your understanding of the *replication operator*, which was covered in the last exercise.

```
module top_module (
input logic a, b, c, d, e,
output logic [24:0] out );
assign out = { {5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}} } ~^ { 5{ a, b, c, d, e } };
endmodule : top_module
```

Note that we’re using the shorthand XNOR operator above (*~^*). Remember that this shorthand notation doesn’t work for NAND and NOR *bitwise* operations, so you can’t use *~&* or *~|*. They will, however, work for the NAND and NOR *reduction *operations. It can also be done the “classical” way, if you prefer:

```
module top_module (
input logic a, b, c, d, e,
output logic [24:0] out );
assign out = ~{ {5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}} } ^ { 5{ a, b, c, d, e } };
endmodule : top_module
```

We could also use intermediate vectors to tidy things up:

```
module top_module (
input logic a, b, c, d, e,
output logic [24:0] out );
// Define internal logic
logic [24:0] vectorA, vectorB;
// Concurrent logic assignments
assign vectorA = { {5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}} };
assign vectorB = { 5{ a, b, c, d, e } };
assign out = vectorA ~^ vectorB;
endmodule : top_module
```