HDLBits – Vectorgates

Build a circuit that has two 3-bit inputs that computes the bitwise-OR of the two vectors, the logical-OR of the two vectors, and the inverse (NOT) of both vectors. Place the inverse of b in the upper half of out_not (i.e., bits [5:3]), and the inverse of a in the lower half.

https://hdlbits.01xz.net/wiki/Vectorgates

This exercise is extremely useful in demonstrating why we should use bitwise operations for signal manipulation and not logical operations. Although they are functionally equivalent for 1-bit signals, if you use the same approach every time, you will never run into issues once vectors are introduced.

module top_module (
  input  logic [2:0] a,
  input  logic [2:0] b,
  output logic [2:0] out_or_bitwise,
  output logic [5:0] out_not,
  output logic out_or_logical );
  // Bitwise assignments
  assign out_or_bitwise = a | b;
  assign out_not        = ~{b, a};
  // Logical assignments
  assign out_or_logical = a || b;
endmodule : top_module

Looking at the simulation waveforms on HDLBits after completing this exercise, note that the only time out_or_logical is equal to 0 is when both the a and b inputs are zero vectors. This is because when performing logical operations, having a single 1 in a vector will cause that vector to be treated as a true. As a result:

// Having a single one in a vector makes it true for logical operations
3'b001 == 3'b010 == 3'b011 == 3'b100 == 3'b101 == 3'b110 == 3'b111 == TRUE
// Only a zero vector will be treated as false for logical operations
3'b000 == FALSE

The misuse of bitwise and logical operations is a common source of bugs in modules dealing with vectors, so make sure that you understand the difference between them. By using bitwise operations for signal manipulation, you won’t run into this issue. I totally haven’t been harping on that point. 🙃