Implement the following circuit. Create two intermediate wires (named anything you want) to connect the AND and OR gates together. Note that the wire that feeds the NOT gate is really wire out, so you do not necessarily need to declare a third wire here. Notice how wires are driven by exactly one source (output of a gate), but can feed multiple inputs.
If you’re following the circuit structure in the diagram, you should end up with four assign statements, as there are four signals that need a value assigned.https://hdlbits.01xz.net/wiki/Wire_decl
There are a bunch of ways to solve this problem. To start, we’ll take a look at a node-based approach and then go from there.
With this approach, we define 3 internal nets, which we’ll call nodeA, nodeB, and nodeC. After nodeC is driven properly, all that we have to do is assign this to out and an inverted version of it to out_n. Note that we’re using bitwise operators since we’re performing signal manipulation.
module top_module ( input logic a, input logic b, input logic c, input logic d, output logic out, output logic out_n ); // Declare circuit nodes logic nodeA, nodeB, nodeC; // Intermediate logic assignments assign nodeA = a & b; assign nodeB = c & d; assign nodeC = nodeA | nodeB; // Output assignments assign out = nodeC; assign out_n = ~nodeC; endmodule : top_module
We can also reduce the lines of code by lumping a bunch of logic together instead. This approach doesn’t tend to scale as designs get more complicated, so it’s usually preferable to use intermediate signals to break the logic up into simpler bits. It also doesn’t cost you anything to have intermediate signals here. However, the best solution for you will largely boil down to your personal preferences.
module top_module ( input logic a, input logic b, input logic c, input logic d, output logic out, output logic out_n ); // Output assignments assign out = (a & b) | (c & d); assign out_n = ~out; endmodule : top_module