HDLBits – Wire

Create a module with one input and one output that behaves like a wire.

Unlike physical wires, wires (and other signals) in Verilog are directional. This means information flows in only one direction, from (usually one) source to the sinks (The source is also often called a driver that drives a value onto a wire). In a Verilog “continuous assignment” (assign left_side = right_side;), the value of the signal on the right side is driven onto the wire on the left side. The assignment is “continuous” because the assignment continues all the time even if the right side’s value changes. A continuous assignment is not a one-time event.

The ports on a module also have a direction (usually input or output). An input port is driven by something from outside the module, while an output port drives something outside. When viewed from inside the module, an input port is a driver or source, while an output port is a sink.

The ports on a module also have a direction (usually input or output). An input port is driven by something from outside the module, while an output port drives something outside. When viewed from inside the module, an input port is a driver or source, while an output port is a sink.

In addition to continuous assignments, Verilog has three other assignment types that are used in procedural blocks, two of which are synthesizable. We won’t be using them until we start using procedural blocks.

Hint: A continuous assignment assigns the right side to the left side continuously, so any change to the RHS is immediately seen in the LHS.

https://hdlbits.01xz.net/wiki/Wire

In order to understand not only this module, but more complicated ones, it will be useful to be able to visualize what a module looks like. Taking a look at Figure 1, by creating a module named top_module, we have made a container which will hold all of its associated logic. The input and output port declarations for in and out create nodes (or connection points) which we can use to get data in and out of our module. Finally, the only logic inside of this top_module container is a wire which connects the input and output ports. This wire is created using a continuous assignment, just like before.

By creating a mental picture of what the module boundaries look like, like in Figure 1, it’s clear that all we need to do is create a wire to connect the input and output ports (which are in and out, respectively).

module top_module (
  input  logic in,
  output logic out );
  assign out = in;
endmodule : top_module