HDLBits SystemVerilog Solutions

Here you can find an index for solutions to the HDLBits exercises using modern SystemVerilog. It will take a while to create clear solutions for all of the exercises and add additional descriptions, so links will be added periodically as I have time.

Getting Started
- Getting Started
- Output Zero

Verilog Language
- Basics
- Vectors
- Modules: Hierarchy
  - Modules
  - Connecting ports by position
  - Connecting ports by name
  - Three modules
  - Modules and vectors
  - Adder 1
  - Adder 2
  - Carry-select adder
  - Adder-subtractor
- Procedures
  - Always blocks (combinational)
  - Always blocks (clocked)
  - If statement
  - If statement latches
  - Case statement
  - Priority encoder
  - Priority encoder with casez
  - Avoiding latches
- More Verilog Features
  - Conditional ternary operator
  - Reduction operators
  - Reduction: Even wider gates
  - Combinational for-loop: Vector reversal 2
  - Combinational for-loop: 255-bit population count
  - Generate for-loop: 100-bit binary adder 2
  - Generate for-loop: 100-digit BCD adder

Circuits
- Combinational Logic
  - Basic Gates
    - Wire
    - GND
    - NOR
    - Another gate
    - Two gates
    - More logic gates
    - 7420 chip
    - Truth tables
    - Two-bit equality
    - Simple circuit A
    - Simple circuit B
    - Combine circuits A and B
    - Ring or vibrate?
    - Thermostat
    - 3-bit population count
    - Gates and vectors
    - Even longer vectors
  - Multiplexers
    - 2-to-1 multiplexer
    - 2-to-1 bus multiplexer
    - 9-to-1 multiplexer
    - 256-to-1 multiplexer
    - 256-to-1 4-bit multiplexer
  - Arithmetic Circuits
    - Half adder
    - Full adder
    - 3-bit binary adder
    - Adder
    - Signed addition overflow
    - 100-bit binary adder
    - 3-digit BCD adder
  - Karnaugh Map to Circuit
    - 3-variable
    - 4-variable
    - 4-variable
    - 4-variable
    - Minimum SOP and POS
    - Karnaugh map [1]
    - Karnaugh map [2]
    - K-map implemented with a multiplexer
  - Sequential Logic
    - D flip-flop
    - D flip-flops
    - DFF with reset
    - DFF with reset value
    - DFF with asynchronous reset
    - DFF with byte enable
    - D Latch
    - DFF [1]
    - DFF [2]
    - DFF+gate
    - Mux and DFF [1]
    - Mux and DFF [2]
    - DFFs and gates
    - Create circuit from truth table
    - Detect an edge
    - Detect both edges
    - Edge capture register
    - Dual-edge triggered flip-flop
  - Counters
    - Four-bit binary counter
    - Decade counter
    - Decade counter again
    - Slow decade counter
    - Counter 1-12
    - Counter 1000
    - 4-digit decimal counter
    - 12-hour clock
  - Shift Registers
    - 4-bit shift register
    - Left/right rotator
    - Left/right arithmetic shift by 1 or 8
    - 5-bit LFSR
    - 3-bit LFSR
    - 32-bit LFSR
    - Shift register [1]
    - Shift register [2]
    - 3-input LUT
  - More Circuits
    - Rule 90
    - Rule 110
    - Conway’s Game of Life 16×16
  - Finite State Machines
    - Simple FSM 1 (asynchronous reset)
    - Simple FSM 1 (synchronous reset)
    - Simple FSM 2 (asynchronous reset)
    - Simple FSM 2 (synchronous reset)
    - Simple state transitions 3
    - Simple one-hot state transitions 3
    - Simple FSM 3 (asynchronous reset)
    - Simple FSM 3 (synchronous reset)
    - Design a Moore FSM
    - Lemmings 1
    - Lemmings 2
    - Lemmings 3
    - Lemmings 4
    - One-hot FSM
    - PS/2 packet parser
    - PS/2 packet parser and datapath
    - Serial receiver
    - Serial receiver and datapath
    - Serial receiver with parity checking
    - Sequence recognition
    - Q8: Design a Mealy FSM
    - Q5a: Serial two’s complementer (Moore FSM)
    - Q5b: Serial two’s complementer (Mealy FSM)
    - Q3a: FSM
    - Q3b: FSM
    - Q3c: FSM logic
    - Q6b: FSM next-state logic
    - Q6c: FSM one-hot next-state logic
    - Q6: FSM
    - Q2a: FSM
    - Q2b: One-hot FSM equations
    - Q2a: FSM
    - Q2b: Another FSM
  - Building Larger Circuits
    - Counter with period 1000
    - 4-bit shift register and down counter
    - FSM: Sequence 1101 recognizer
    - FSM: Enable shift register
    - FSM: The complete FSM
    - The complete timer
    - FSM: One-hot logic equations

Verification: Reading Simulations
- Finding bugs in code
  - Mux
  - NAND
  - Mux
  - Add/sub
  - Case statement
- Build a circuit from a simulation waveform
  - Combinational circuit 1
  - Combinational circuit 2
  - Combinational circuit 3
  - Combinational circuit 4
  - Combinational circuit 5
  - Combinational circuit 6
  - Sequential circuit 7
  - Sequential circuit 8
  - Sequential circuit 9
  - Sequential circuit 10

Verification: Writing Testbenches
- Clock
- Testbench1
- AND gate
- Testbench2
- T flip-flop

CS450
- . [1]
- . [2]
- . [3]
- . [4]