In this exercise, you will create a circuit with two levels of hierarchy. Your top_module will instantiate two copies of add16 (provided), each of which will instantiate 16 copies of add1 (which you must write). Thus, you must write two modules: top_module and add1. Like module_add, you are given a module add16 that performs a 16-bit addition. You must instantiate two of them to create a 32-bit adder. One add16 module […]

You are given a module add16 that performs a 16-bit addition. Instantiate two of them to create a 32-bit adder. One add16 module computes the lower 16 bits of the addition result, while the second add16 module computes the upper 16 bits of the result, after receiving the carry-out from the first adder. Your 32-bit adder does […]

This exercise is an extension of module_shift. Instead of module ports being only single pins, we now have modules with vectors as ports, to which you will attach wire vectors instead of plain wires. Like everywhere else in Verilog, the vector length of the port does not have to match the wire connecting to it, but […]

aYou are given a module my_dff with two inputs and one output (that implements a D flip-flop). Instantiate three of them, then chain them together to make a shift register of length 3. The clk port needs to be connected to all instances. The module provided to you is: module my_dff ( input clk, input d, output q ); Note […]

This problem is similar to module. You are given a module named mod_a that has 2 outputs and 4 inputs, in some order. You must connect the 6 ports by name to your top-level module’s ports: See the HDLBits page for a diagram and table. https://hdlbits.01xz.net/wiki/Module_name Ah, now we get to connect ports by name. My world makes sense again […]

This problem is similar to the previous one (module). You are given a module named mod_a that has 2 outputs and 4 inputs, in that order. You must connect the 6 ports by position to your top-level module’s ports out1, out2, a, b, c, and d, in that order. You are given the following module: See the HDLBits page for a diagram. https://hdlbits.01xz.net/wiki/Module_pos There’s not […]

By now, you’re familiar with a module, which is a circuit that interacts with its outside through input and output ports. Larger, more complex circuits are built by composing bigger modules out of smaller modules and other pieces (such as assign statements and always blocks) connected together. This forms a hierarchy, as modules can contain instances of other […]

Given five 1-bit signals (a, b, c, d, and e), compute all 25 pairwise one-bit comparisons in the 25-bit output vector. The output should be 1 if the two bits being compared are equal. out[24] = ~ a ^ a; // a == a, so out[24] is always 1. out[23] = ~ a ^ b; […]

Build a circuit that sign-extends an 8-bit number to 32 bits. This requires a concatenation of 24 copies of the sign bit (i.e., replicate bit[7] 24 times) followed by the 8-bit number itself. https://hdlbits.01xz.net/wiki/Vector4 The main takeaway for this exercise is that the replication operator can be used to duplicate signals to aid in signal […]

Given an 8-bit input vector [7:0], reverse its bit ordering. Hint: assign out[7:0] = in[0:7]; does not work because Verilog does not allow vector bit ordering to be flipped. Hint: The concatenation operator may save a bit of coding, allowing for 1 assign statement instead of 8. https://hdlbits.01xz.net/wiki/Vectorr So all we have to do is perform […]