Given several input vectors, concatenate them together then split them up into several output vectors. There are six 5-bit input vectors: a, b, c, d, e, and f, for a total of 30 bits of input. There are four 8-bit output vectors: w, x, y, and z, for 32 bits of output. The output should […]

Build a combinational circuit with four inputs, in[3:0]. There are 3 outputs: out_and: output of a 4-input AND gate.out_or: output of a 4-input OR gate.out_xor: output of a 4-input XOR gate. https://hdlbits.01xz.net/wiki/Gates4 The point of this exercise is to demonstrate the use of the reduction operators, which can be used to prevent having to make logic […]

Build a circuit that has two 3-bit inputs that computes the bitwise-OR of the two vectors, the logical-OR of the two vectors, and the inverse (NOT) of both vectors. Place the inverse of b in the upper half of out_not (i.e., bits [5:3]), and the inverse of a in the lower half. https://hdlbits.01xz.net/wiki/Vectorgates This exercise is extremely useful in demonstrating why […]

A 32-bit vector can be viewed as containing 4 bytes (bits [31:24], [23:16], etc.). Build a circuit that will reverse the byte ordering of the 4-byte word. This operation is often used when the endianness of a piece of data needs to be swapped, for example between little-endian x86 systems and the big-endian formats used in many Internet protocols. […]

Build a combinational circuit that splits an input half-word (16 bits, [15:0] ) into lower [7:0] and upper [15:8] bytes. https://hdlbits.01xz.net/wiki/Vector1 There is a lot of great information on the HDLBits page for this exercise, so make sure that you understand everything there. Note that we will only be using the logic datatype in these […]

Build a circuit that has one 3-bit input, then outputs the same vector, and also splits it into three separate 1-bit outputs. Connect output o0 to the input vector’s position 0, o1 to position 1, etc. In a diagram, a tick mark with a number next to it indicates the width of the vector (or “bus”), rather than drawing […]

The 7458 is a chip with four AND gates and two OR gates. This problem is slightly more complex than 7420. Create a module with the same functionality as the 7458 chip. It has 10 inputs and 2 outputs. You may choose to use an assign statement to drive each of the output wires, or you may choose […]

Implement the following circuit. Create two intermediate wires (named anything you want) to connect the AND and OR gates together. Note that the wire that feeds the NOT gate is really wire out, so you do not necessarily need to declare a third wire here. Notice how wires are driven by exactly one source (output of […]

Create a module that implements an XNOR gate. Note: The bitwise-XOR operator is ^. There is no logical-XOR operator. https://hdlbits.01xz.net/wiki/Xnorgate This exercise is very similar to the NOR gate problem. We can implement the XNOR logic various ways. First, we’ll approach it the same way that we approached the NOR gate problem: There is also shorthand […]

Create a module that implements a NOR gate. A NOR gate is an OR gate with its output inverted. A NOR function needs two operators when written in Verilog. An assign statement drives a wire (or “net”, as it’s more formally called) with a value. This value can be as complex a function as you want, as […]