Create a module that implements an AND gate.
This circuit now has three wires (
balready have values driven onto them by the input ports. But wire
outcurrently is not driven by anything. Write an
assignstatement that drives
outwith the AND of signals
Note that this circuit is very similar to the NOT gate, just with one more input. If it sounds different, it’s because I’ve started describing signals as being driven (has a known value determined by something attached to it) or not driven by something.
Input wiresare driven by something outside the module.
assignstatements will drive a logic level onto a wire. As you might expect, a wire cannot have more than one driver (what is its logic level if there is?), and a wire that has no drivers will have an undefined value (often treated as 0 when synthesizing hardware).
Hint: Verilog has separate bitwise-AND (https://hdlbits.01xz.net/wiki/Andgate
&) and logical-AND (
&&) operators, like C. Since we’re working with a one-bit here, it doesn’t matter which we choose.
This exercise is extremely similar to the inverter problem. If you haven’t read that solution, you should check it out since it will give you a powerful general rule of thumb for when to use logical (&&) and bitwise (&) operators. Although a logical operator (&&) will also work here since we’re working with 1-bit signals, the preferred solution is:
module top_module ( input logic a, input logic b, output logic out ); // Use bitwise operators for signal manipulation assign out = a & b; endmodule : top_module