By now, you’re familiar with a
module, which is a circuit that interacts with its outside through input and output ports. Larger, more complex circuits are built by composing bigger modules out of smaller modules and other pieces (such as assign statements and always blocks) connected together. This forms a hierarchy, as modules can contain instances of other modules.
The figure below shows a very simple circuit with a sub-module. In this exercise, create one instance of module
<em>mod_a</em>, then connect the module’s three pins (
out) to your top-level module’s three ports (wires
out). The module
mod_ais provided for you — you must instantiate it.
Note: We use the logic datatype and not the wire datatype in these SystemVerilog solutions. The wire/tri types are only used in special situations in modern SystemVerilog. The legacy reg datatype should never be used in modern SystemVerilog.https://hdlbits.01xz.net/wiki/Module
The point of this exercise is to introduce module instantiation, which is extremely useful when working with larger designs. Being able to partition our design into a hierarchy of modules allows us to keep modules short(-ish), while also encapsulating similar design functionality. This is much better than having one massive module that performs a bunch of different functions.
It’s mentioned on the HDLBits page that you can instantiate a module by name or by position. As a general rule, always instantiate modules by name. Instantiating modules by position is great until the ports of the module that you’re instantiating change. Having the positional dependency that is introduced by instantiating modules by position makes it much more annoying to maintain a design as it changes and grows.
This exercise can be completed simply by instantiating the mod_a module by name. The _i is short for instance when referencing this mod_a module.
module top_module ( input logic a, b, output logic out ); mod_a mod_a_i ( .in1(a), .in2(b), .out(out) ); endmodule : top_module