HDLBits – Norgate

Create a module that implements a NOR gate. A NOR gate is an OR gate with its output inverted. A NOR function needs two operators when written in Verilog.

An assign statement drives a wire (or “net”, as it’s more formally called) with a value. This value can be as complex a function as you want, as long as it’s a combinational (i.e., memory-less, with no hidden state) function. An assign statement is a continuous assignment because the output is “recomputed” whenever any of its inputs change, forever, much like a simple logic gate.

Hint: Verilog has separate bitwise-OR (|) and logical-OR (||) operators, like C. Since we’re working with a one-bit here, it doesn’t matter which we choose.

https://hdlbits.01xz.net/wiki/Norgate

This problem is also very similar to the inverter problem, so make sure to take a look at that solution if you haven’t already. The only difference here is that we’re combining two operations to form a NOR gate: NOT (~) and OR (|). As was described in the solution to the inverter problem, linked above, we should use bitwise operators here since we’re performing signal manipulation.

module top_module (
input  logic a,
input  logic b,
output logic out );

// Use bitwise operators for signal manipulation
assign out = ~(a | b);

endmodule : top_module