# HDLBits – Step One

We’re going to start with a small bit of HDL to get familiar with the interface used by HDLBits. Here’s the description of the circuit you need to build for this exercise:

Build a circuit with no inputs and one output. That output should always drive 1 (or logic high).

Hint: We want to assign 1 to the output one.

https://hdlbits.01xz.net/wiki/Step_one

The main takeaway from this exercise is that most modules will have a number of input and output ports. There are other ways of passing signals around in a design in SystemVerilog, but those aren’t important right now. In this case, there is only one output, one. We say that this is a 1-bit output port.

module top_module (
output logic one );

// The '1 value will fill an n-bit vector with ones at every bit position
assign one = '1;

endmodule : top_module

The exercise is completed by making a continuous assignment, which is done using the assign keyword. This assign statement will create a wire that connects the output port, one, to a constant high value of 1. Therefore, the output port, one, and this constant high value of 1 can be viewed as nodes which need to be connected. The assign statement here is our method of connecting the dots by creating a wire that connects them.

There are also other values that can be assigned to the one output port in order to complete this exercise:

// Assign a 1-bit binary value (1'b1) to the 1-bit output port (one)
assign one = 1'b1;

Although this design style is perfectly correct and technically more explicit than the ‘1 assignment above, it can make code inspection cumbersome in more complicated modules and also requires more keystrokes, which doesn’t bode well for laziness. Another alternative solution is:

// Assign a 32-bit vector (32'd1) to the 1-bit output port (one)
// This will be truncated automatically
assign one = 1;

It’s important to understand that by assigning 1 to the one output port, a 32-bit logic vector is being assigned to the 1-bit output port, one. As a result, the top 31 bits of this vector will need to be truncated by Verilog, preserving only the least significant bit (LSB). This practice should be avoided since this will result in noise being added to the linting report for a design. This makes it harder to identify the real issues and is also very annoying if someone asks you to clean all of them up! I definitely don’t know anything about that. 🙃