HDLBits – Vector3

Given several input vectors, concatenate them together then split them up into several output vectors. There are six 5-bit input vectors: a, b, c, d, e, and f, for a total of 30 bits of input. There are four 8-bit output vectors: w, x, y, and z, for 32 bits of output. The output should be a concatenation of the input vectors followed by two 1 bits.

Note: See the HDLBits link for a diagram.


We’ve seen a handful of concatenation examples in previous exercises and nothing will change here. There are a couple of additional points to make though:

  • Unsized constants cannot be used in concatenations
  • Dynamically sized constants (‘1, ‘0, ‘x, ‘z) only count as 1-bit values and cannot be used to fill out or pad a concatenation statement

It might seem at first that you should use 4 separate assign statements to solve this one (for w, x, y, and z), but that ends up overcomplicating the problem. Instead, we can use concatenation on both sides of a single assign statement:

module top_module (
  input  logic [4:0] a, b, c, d, e, f,
  output logic [7:0] w, x, y, z );
  // Assign 30 input bits, followed by 2'b11, to 32 output bits
  assign {w, x, y, z} = {a, b, c, d, e, f, 2'b11};
endmodule : top_module

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