HDLBits – Vectorr

Given an 8-bit input vector [7:0], reverse its bit ordering.

Hint: assign out[7:0] = in[0:7]; does not work because Verilog does not allow vector bit ordering to be flipped.

Hint: The concatenation operator may save a bit of coding, allowing for 1 assign statement instead of 8.

https://hdlbits.01xz.net/wiki/Vectorr

So all we have to do is perform bit-reversal of the input vector. One potential idea might be to try to assign the little-endian input vector to a big-endian internal vector in order to reverse the bits. Will this work?

module top_module (
  input  logic [7:0] in,
  output logic [7:0] out );
  // Define internal logic
  logic [0:7] reverse;
  // Assign the little-endian input to a big-endian vector
  // Will this perform bit reversal?
  assign reverse = in;
    
  // Output assignment
  assign out = in;  
    
endmodule : top_module

This solution will not work, since when assigning vectors, they are connected MSB-to-MSB. In the end, the result will be as follows:

assign reverse = { in[7], in[6], in[5], in[4], in[3], in[2], in[1], in[0] };
assign out     = { reverse[0], reverse[1], reverse[2], reverse[3], reverse[4], reverse[5], reverse[6], reverse[7] };

Since the MSB of reverse is located at index 0, the above approach to bit-reversal will not work. Luckily, we can still rely on the tried and true concatenation method:

module top_module (
  input  logic [7:0] in,
  output logic [7:0] out );
    
  // Bit-reversal with concatenation
  assign out = { in[0], in[1], in[2], in[3], in[4], in[5], in[6], in[7] };  
    
endmodule : top_module

We could also use a for loop with a generate block to achieve this same approach. Though this is definitely overkill here, this could be very useful for much larger vectors:

module top_module (
  input  logic [7:0] in,
  output logic [7:0] out );
  // Define a variable for the generate loop to iterate over
  genvar i;
    
  // Bit-reversal using a for loop (useful for large vectors)
  // This will generate 8 total assign statements
  generate
    for (i=0; i <= 7; i++) begin : bit_reversal
      assign out[7-i] = in[i];
    end
  endgenerate    
    
endmodule : top_module

We could make this more generic using a parameter. By adding a parameter that allows the size of the input and output vectors to be changed, we have created a reuse module that can be instantiated whenever we need to reverse vectors in the future:

module top_module 
  #( parameter LENGTH = 8 )
   (
     input  logic [LENGTH-1:0] in,
     output logic [LENGTH-1:0] out );
  // Define a variable for the generate loop to iterate over
  genvar i;
    
  // Bit-reversal using a for loop (useful for large vectors)
  // This will generate 8 total assign statements
  generate
    for (i=0; i <= LENGTH-1; i++) begin : bit_reversal
      assign out[LENGTH-1-i] = in[i];
    end
  endgenerate    
    
endmodule : top_module