Build a circuit with no inputs and one output that outputs a constant 0.
Now that you’ve worked through the previous problem, let’s see if you can do a simple problem without the hints.
Fun fact: For Quartus synthesis, not assigning a value to a signal usually results in 0. This problem is actually easier than the previous one. This is bad practice, never do this.
Note: Although it is mentioned on the HDLBits website, using Verilog-1995 port declarations is bad practice and should never be done either.https://hdlbits.01xz.net/wiki/Zero
This is basically the same exercise as the last one, so see that solution for more details. In line with my solution coding guidelines, I will be using dynamically sized assignments (‘0, ‘1, ‘x, ‘z) for this and all subsequent solutions, unless otherwise noted:
module top_module ( output logic zero ); // The '0 value will fill an n-bit vector with zeros at every bit position assign zero = '0; endmodule : top_module